Versal Interface Debugging Considerations - 2025.2 English - UG908

Vivado Design Suite User Guide: Programming and Debugging (UG908)

Document ID
UG908
Release Date
2025-11-20
Version
2025.2 English

The Versal AXI4-Stream ILA (Versal ILA) supports the probing AXI4 interfaces when used in the Vivado IP integrator and when instantiated in an RTL design. This mode can be useful when it needed to probe an AXI interface that is not contained within an IP integrator Block Design, such as when Modular NoC is used. This mode can be accessed by generating an instance of the Versal ILA from the standard IP catalog and then changing the Versal ILAs mode to Interface or Mixed in the IP configuration GUI.

Important: When the Versal ILA's interface mode is used in RTL designs, the designer is responsible for correctly configuring all interface parameters that can have a varying size (for example, address width or data width) for the given interface. It is important to review all configured IP parameters for correctness before continuing debug.