The System Integrated Logic Analyzer (System ILA) IP core is a logic analyzer that allows you to perform in-system debugging of post-implemented designs on an FPGA device. Use this IP when you need to monitor interfaces and signals in the IP integrator Block Design. You can also use this feature to trigger interface and signal related hardware events and capture data at system speeds. This ensures the intuitive presentation of interface events in the Hardware Manager when debugging the design on an FPGA or adaptive SoC. This IP offers AXI interface debug and monitoring capability along with AXI4-MM and AXI4-Stream protocol checking.
Because the System ILA core is synchronous to the design being monitored,
all design clock constraints applied to your design are also applied to the core's
components. You can find detailed documentation on the System ILA core IP in the
System
Integrated Logic Analyzer LogiCORE IP Product Guide (PG261).
Note: On AMD Versal™
devices the System ILA functionality is
available using the Versal ILA core.