The JTAG-to-AXI Master debug feature generates AXI transactions to interact with AXI4 and AXI4-Lite slave cores in a system running in hardware. AMD recommends that you use this core to generate AXI transactions and debug/drive AXI signals internal to an FPGA at runtime. You can use this core in designs without processors as well.
The IP catalog lists this core under the Debug category. Debugging Logic Designs in Hardware of this guide has more details about the JTAG-to-AXI Master core and its usage methodology in the Vivado Design Suite. You can find detailed documentation on the JTAG-to-AXI IP core in the JTAG to AXI Master LogiCORE IP Product Guide (PG174).