The Integrated Bit Error Ratio Tester (IBERT) Serial Analyzer design enables in-system serial I/O validation and debug. This allows you to measure and optimize your high-speed serial I/O links in your FPGA-based system. AMD recommends the IBERT Serial Analyzer design to address a range of in-system debug and validation problems. For example, simple clocking and connectivity issues, complex margin analysis, and channel optimization issues.
AMD recommends the IBERT Serial Analyzer design to measure the quality of a signal after you apply a receiver equalization to the received signal. This ensures that you are measuring at the optimal point in the TX-to-RX channel thereby ensuring real and accurate data. Access this design by selecting, configuring, and generating the IBERT core from the IP catalog and selecting the Open Example Design feature of this core. See Serial I/O Hardware Debugging Flows and Debugging the Serial I/O Design in Hardware for more details on the IBERT core and its usage methodology in the Vivado Design Suite.