Considerations for Segmented Configuration - 2025.2 English - UG908

Vivado Design Suite User Guide: Programming and Debugging (UG908)
Document ID
UG908
Release Date
2025-11-20
Version
2025.2 English

The segmented configuration feature for Versal enables booting the processors in a Versal device and accessing DDR memory before the programmable logic (PL) is configured. This enables DDR-based software (for example, Linux) to start first, while the PL can be configured later from any primary or secondary boot device or a DDR image —offering flexibility similar to AMD Zynq UltraScale+ MPSoCs. When enabled, Vivado automatically identifies the NoC path segments for the initial boot image, and generate two PDIs —one for boot and another for the PL. The entire PL remains dynamic and can be fully reloaded while the operating system and DDR access stay active.

When this flow is used, many of the steps in this document are still applicable with small modifications.

  1. Any features that use the PL such as the Integrated Logic Analyzer (ILA) or Virtual Input/Output (VIO) cores require both the boot and PL PDIs to be loaded into the device.
  2. Programming Configuration Memory Devices requires both the boot PDI and PL PDIs in addition to the Initialization PDI.
Important: If segmented configuration is used on a device where it is not the default flow (for example, first generation Versal devices), you can enable segmented configuration features in Vivado Hardware Manager by setting the parameter labtools.enableSegmentedConfigFlow to 1 before launching the Vivado Hardware Manager.