Versal devices use the AXI4 Debug Hub, similar to the debug hub in previous architectures and provides connectivity between the Versal Control, Interface, and Processing (CIPS) IP and the debug cores in the design. In previous architectures Vivado inserts this core automatically without user intervention. It is also possible to manually instantiate the AXI4 Debug Hub. Manual instantiation is only recommended if using DFX, or the design's addressing scheme that requires setting a manual address for the AXI4 Debug Hub.
The AXI4 Debug Hub uses the NoC to export data from the design to the PMC. The required NoC bandwidth for the Debug Hub path is small. Use the default value of 5 Mb/s for both read and write.