AXI4 Debug Hub Connectivity - 2025.1 English - UG908

Vivado Design Suite User Guide: Programming and Debugging (UG908)
Document ID
UG908
Release Date
2025-05-29
Version
2025.1 English

To use the AMD Vivado™ debug cores, the design must contain an AXI4 Debug Hub. The AXI4 Debug Hub connects an AXI4 interface of the CIPS with the AXI4-Stream interface. The interface connects to Vivado debug cores, which includes the following types of cores:

  • AXI4-Stream Integrated Logic Analyzer (AXIS-ILA)
  • AXI4-Stream Virtual Input/Output (AXIS-VIO)
  • PCI Express® Link Debugger
Table 1. AXI4 Debug Hub Auto-Insertion
AXI4 Debug Hub Connectivity Debug Flow
Automatic AXI4 Debug Hub post-synthesis netlist insertion and connection. This method is recommended for most use cases as it provides the most flexibility.
  1. During opt_design the Vivado debug flow detects if the design contains any debug cores that require AXI4 Debug Hub connectivity. The Vivado debug flow also detects if the design contains an instance of the Control, Interface, and Processing (CIPS) IP.
  2. The Vivado debug flow inserts an instance of the AXI4 Debug Hub into the synthesized netlist and automatically connects it to the debug cores used in the design.
Note: This method cannot be used on designs that use Dynamic Function eXchange (DFX).
Manual AXI4 Debug Hub instantiation, automatic post-synthesis netlist debug core connection. This method should be used when it is desired to manually assign the address used by the AXI4 Debug Hub or when Dynamic Function eXchange (DFX) is used. In this case the design should have a manually instantiated AXI4 Debug Hub with a connection to an AXI4 master from the Control, Interface, and Processing (CIPS) IP.
  1. During opt_designthe Vivado debug flow detects if the design contains any debug cores that require AXI4 Debug Hub Connectivity. The Vivado debug flow also detects if the design contains an instance of the Control, Interface, and Processing (CIPS) IP.
  2. The Vivado debug flow locates the manually added AXI4 Debug Hub. This instance of the AXI4 Debug Hub is replaced with an AXI4 Debug Hub configured with a suitable number of AXI4-Stream interfaces to connect to each debug core used in the design.
    Note: The AXI4 Debug Hub that is replaced by the Vivado debug flow in the previous steps retains the user specified address and properties.
Manual AXI4 Debug Hub instantiation, manual debug core connection. This method should be used when it is desired to manually define all connectivity between the AXI4 Debug Hub, CIPS, and all debug cores in the design. This method can also be used when the design uses Dynamic Function eXchange (DFX).
  1. When building the design, one, or more instances of the AXI4 Debug Hub are added to the design with connectivity to an appropriate AXI4 master on the CIPS IP.
  2. The AXI4 Debug Hub should be customized to include the exact number of AXI4-Stream interfaces as there are debug cores in the design.
  3. Each debug core in the design should have the option to enable AXI4-Stream ports for manual connectivity turned on.
  4. It is the user's responsibility to connect each debug core's AXI4-Stream master and slave to a corresponding slave and master on the AXI4 Debug Hub.
Note: When manually connecting the AXI4 Debug Hub it is recommended to use the PMC NoC interface as this is a dedicated path to the debug packet controller. While use of the FPD or LPD interfaces is also possible, the extended address ranges 0x004_0000_0000 (8G) and 0x400_0000_0000 (1T) are not supported.