Network on Chip - Network on Chip - 2025.2 English

Network on Chip - Network on Chip - 2025.2 English - UG907

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

Document ID

UG907

Release Date

2025-11-20

Version

2025.2 English

The AMD Versal™ Network on Chip (NoC) is a high bandwidth interface within a Versal adaptive SoC. It allows high bandwidth and Quality of Service (QoS) support for all resources on a Versal device. NoC is an AXI-interconnecting network used for sharing the data among IP endpoints in the programmable logic (PL), the processing system (PS), and other hard blocks. A single physical NoC channel can be shared by traffic with different latency or bandwidth requirements. The NoC is configured using the AXI NoC IP wizards to setup the required connections and the QoS. Report power uses the output of the NoC compiler automatically to estimate the NoC power. For more information, see Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313). The following figure shows the NoC view in the AMD Vivado™ IP integrator:

Figure 1. NoC View

The following figure shows the NoC QoS view:

Figure 2. NoC QoS View

The following figure shows the NoC Power view generated by the report power command:

Figure 3. NoC Power View

Note: The unused portions of NoC clock networks are automatically gated to save power on monolithic devices only. Due to limitations, NoC clock networks cannot be gated for SSI devices and devices using multiple DFX partitions, including monolithic devices.

Vivado and Vitis generate .xpe files during implementation runs as well as during NoC compiler runs. These .xpe files can be imported to the PDM tool using import functionality for performing detailed what-if analysis. For more information, see Power Design Manager User Guide (UG1556). The generated .xpe file can be found in the following path (in the project directory): project_1.gen/sources_1/common/nsln/NOC_Power.xpe.