Multiport RAM - 2024.2 English - UG907

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

Document ID
UG907
Release Date
2024-11-18
Version
2024.2 English

The Multiport RAM (MPRAM) block is supported for XCVP1002 and XCVP1052 devices. MPRAM block has up to eight memory units, each of which is made up of 20 single ported memory macros of 2048x128 b. Therefore, the size of each memory unit is up to 5 MB. A memory unit consists of two local read and one local write (128-bit) ports, which can only access the associated memory unit.

Refer to Multiport RAM LogiCORE IP Product Guide (PG415) for more information.

Figure 1. MPRAM

Power parameters can be configured from Power Estimation Tab of Multiport RAM LogiCORE IP.

Interface Clock Frequency
Clock frequency of the clock supplied to the core in MHz. This is the frequency at which the interfaces run.
Toggle Rate (%)
User-defined overall data toggle rate for all interface
Global/Unit Interface - Active Duty Cycles (%)
User-defined Read and Write active duty cycle of the interface as a percentage, where 100% means the interface is active on every cycle and 0% means the interface is unused.
Figure 2. MPRAM Power Configuration
Note: Combined activity duty cycle is derived from the average active duty cycle and toggle rate that you provide IP creation.