AMD Versal™ device IOs are categorized into the following two categories:
- HDIO
- It is designed as a high density IO that is cost effective and flexible for implementation. HDIO is intended to cover IO standards not offered by XPIO with maximum VCCO beyond 1.5V.
- XPIO
- It supports IO standards with maximum VCCO of 1.5V. XPIO is designed to replace HPIO (AMD UltraScale+™ ) and PS dedicated DDR memory interface IO (PS-DDRIO). It is important to define proper IO standard for an accurate on-chip and off-chip power estimation for IO interfaces. If an IO standard is not defined then zero power is reported.
- X5IO
- The X5IO pins are grouped in banks of 32 input and output buffers (IOB) (16 pairs), with each IOB having direct access to the X5IO PHY logic. The X5IO logic is used for the integrated DDRMC, soft memory controllers, MIPI (C-PHY and D-PHY) and custom high-performance I/O interfaces. The X5IO only provides access to the PL fabric when bypassing the PHY.
For more information, see Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).