DDR Memory Controller - 2025.1 English - UG907

AMD Versal™ Adaptive SoC devices have up to 4 hardened DDR memory controllers, accessible from the PS or the PL through the NoC. Each memory controller instance is connected to the NoC using four system ports. Each of these ports are bi-directional 128-bit data paths with three traffic types. A maximum data rate of 4266 Mb/s, per data pin, is supported for LPDDR4/4X and a maximum data rate of 3200 Mb/s is supported for DDR4/4E. For more information, see Memory Interface Controller section of Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956). The DDR Memory Controller (DDRMC) configuration is performed using NoC IP and the dependent power parameters are computed using NoC compiler. For more information, see Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313). The following figure shows the DDRMC Power View.

Figure 1. DDRMC Power View

Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 devices support DDR5, LPDDR5.

Figure 2. DDR5