AI Engine-ML (AIE-ML) is available in Versal AI Edge Series and a few Versal AI Core Series devices. The compute tiles are similar to AI-Engine tiles with additional support for BFloat data type. AI-Engine-ML has additional shared memory tiles for improved performance and data movement.
The maximum total supported memory by memory tile is up to 38 MB across AIE Array, depending on the device. Memory Tile memory banks have 512 KB SRAM, arranged in 16 physical banks, each 128-bit wide and 2K words deep. Report_power can generate a .xpe file, which you can import in PDM. All the configuration parameters are passed on from Vitis design sources.
For more information, refer to Versal Adaptive SoC AIE-ML Architecture Manual (AM020).
Versal AI Edge Series Gen 2 supports AI Engine-ML_v2. If a design has AI Engine-MLv2, Vivado report_power reports the estimated power for the configuration. You can export the .xpe file from Vivado to import in the PDM tool for a what-if analysis.
AI Engine, AI Engine-ML, and AI Engine-ML for Versal AI Edge Series Gen 2 now support most data types. Any Vitis data type without a dedicated power model falls back to the INT16 model - for example, INT32 is mapped to INT16. The same applies when a single AI Engine tile hosts multiple kernels operating on different data types: the tile's power is reported using the INT16 model.