Using the Schematic Window - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

The schematic is a graphical representation of the netlist that includes the following:

  • View a graphical representation for the netlist.
  • Review gates, hierarchies, and connectivity.
  • Trace and expand cones of logic.
  • Analyze the design.
  • Better understand what is happening inside the design.

At the RTL level in Elaborated Design, the schematic shows how the tool has interpreted your code. In Synthesize Design and Implemented Design, it displays the netlist generated by the synthesis tool.

Use the following steps to open and interact with the schematic:

  1. Select Tools > Schematic.
  2. If nothing is selected, the schematic displays the cells, hierarchy, and connectivity at the top level of the design.

    Tip: You can create a simpler schematic by first selecting cell, net, pin, or port objects, then generating the schematic from those selected items.


  3. Use the following methods to navigate the schematic:
    • Click + to expand the gates in the hierarchy.
    • Double-click ports or cells to trace connectivity.
    • Right-click and select Schematic from the popup menu.
    • Use ← and → to switch views.

After implementation, the schematic is the easiest way to visualize the cells in a timing path. Select the path, then open the schematic to view the related cells and nets.

For more details, see Using the Schematic Window in the Vivado Design Suite User Guide: Using the Vivado IDE (UG893).

Figure 1. Schematic with Timing Path

To analyze a selected cell in the schematic, follow these steps:

  1. Right-click the cell and select Select Leaf Cell Parents from the popup menu to identify the relevant levels of hierarchy.

  2. Use the Highlight or Mark commands to track leaf cells of interest.
  3. Apply color coding to the selected cells to clearly distinguish between logic from the original path and added logic.
Figure 2. Schematic with Timing Path Marked