Use the Netlist window to view the design hierarchy as it exists in the netlist, processed by the synthesis tools. This window helps you explore the logical hierarchy of the design.
Depending on your synthesis settings, the netlist hierarchy can match the original RTL, or contain no hierarchy. When run with the default settings, synthesis preserves your RTL hierarchy while optimizing logic, resulting in an optimal netlist for implementation.
The netlist hierarchy appears as a folder tree. Expanding the hierarchy folder reveals the following:
- A Nets folder for nets at that level
- A Leaf Cells folder if hardware primitive instances exist at that level
- A folder for any hierarchies instantiated at that level
The icons next to the cells show information about the state of the design.
Refer to Using the Netlist Window in the
Vivado
Design Suite User Guide: Using the Vivado IDE (UG893) for details. For more
information on the KEEP_HIERARCHY property and -flatten_hierarchy command switch, refer to the
Vivado
Design Suite User Guide: Synthesis (UG901).
Cell Properties
Select Cell Properties after you select a hierarchy to view detailed information. Filter the information using the category buttons at the bottom of the window.
Select Statistics to view the following information:
- Primitive usage for the full hierarchical branch, grouped in higher-level buckets
- Number of nets crossing the hierarchy boundary
- Clock details, including whether the clock uses global routing and the number of its loads in the current hierarchical branch
If you floorplan the design, similar properties appear for the Pblock.