Using the Elaborated View to Optimize the RTL - 2025.2 English - UG906

When analyzing timing results after any implementation step using report_timing, report_timing_summary, or report_design_analysis, review the structure of critical paths to determine whether they can be mapped to logic primitives more efficiently by modifying the RTL, using synthesis attributes, or applying different synthesis options. This is especially important for paths with a high number of logic levels, which can strain the implementation tools and limit overall design performance. For more information about the Linter tool, see the Vivado Design Suite User Guide: Synthesis (UG901)

If you find a critical path with many logic levels, assess whether the functionality truly requires that logic depth. Determining the optimal number of logic levels depends on both your knowledge of the design and RTL optimization in general. Analyzing the post-synthesis optimized netlist to pinpoint RTL inefficiencies can be complex.

In project mode, the AMD Vivado™ Integrated Design Environment (IDE) provides a cross-probing mechanism between the synthesized or implemented design and the elaborated design to simplify this analysis.

1. Open both the synthesized or implemented design and the elaborated design in memory.
2. In the synthesized or implemented design view, select the timing path and show its schematics by pressing F4 key.
3. In the Flow Navigator pane, select Elaborated Design. The RTL cells corresponding to the timing path are selected automatically. You can then:
   • Press F4 to open the RTL schematics and view the same path in the elaborated view.
   • Trace from the endpoint pin back to the startpoint cell.