When you integrate RTL into a design, visualizing the design inside the device can help you understand how it is structured. Viewing how blocks interconnect with each other and with the I/O pinout after synthesis provides valuable insight.
To view the interconnect, generate a top-level floorplan using Pblocks on upper levels of hierarchy.
Pblocks can be more than 100 percent full during analysis, but not during implementation. Overfilling a Pblock during analysis makes it smaller on the device. This is a useful technique for seeing the relative size of your top-level blocks and how they occupy the device.