Timing Violations - Timing Violations - 2026.1 English - UG906

While fixing the worst timing violation often improves overall QoR, you must also review other critical paths, as they frequently contribute to timing closure challenges.

Follow these steps to identify and address timing violations using Report Design Analysis:

1. Run the following command to generate the Setup Path Characteristics table. In this example, Vivado reports the 50 worst setup timing paths.

   report_design_analysis -max_paths 50 -setup

   
   
   
2. Review the table to isolate which characteristics are introducing timing violations for each path.
3. If high logic delay percentage (Logic Delay) causes the violation, use the following checks:
   • Check whether the path has many logic levels (Logic Levels).
   • Determine whether constraints or attributes prevent logic optimization, such as DONT_TOUCH or MARK_DEBUG.
   • Identify cells with high logic delay, such as RAMB or DSP cells.
   • Evaluate whether the path requirement is too tight for the current path topology (Requirement).
4. If high net delay percentage (Net Delay) causes the violation, use the following checks:
   • Look for high fanout nets (High Fanout and Cumulative Fanout).
   • Check whether cells are belong to several Pblocks that can place them far apart (Pblocks).
   • Check whether cells are physically far apart (Bounding Box Size and Clock Region Distance).
   • For SSI devices, check whether nets cross SLR boundaries (SLR Crossings).
   • Investigate unusually high net delay values when placement appears correct; refer to Congestion for reference.
5. If the violation is due to a missing pipeline register in a RAMB or DSP cell, verify that you enabled pipeline registers for RAMBs or DSP cells.
6. If high skew causes the violation (Clock Skew), use the following checks:
   • Check whether the skew is less than ﹣0.5 ns for setup.
   • Check whether clock skew is greater than 0.5 ns for hold.
   • Check whether the path is a clock domain crossing path (Start Point Clock and End Point Clock).
   • Determine whether the clocks are synchronous or asynchronous (Clock Relationship).
   • Check whether the path crosses I/O columns (I/O Crossings).
7. Review the Logic Level Distribution table for the worst 1000 paths to identify long paths in the design.
   
   
8. Eliminate longer paths where possible to improve overall QoR. Based on your findings, improve the netlist by modifying the RTL, changing synthesis options, or adjusting timing and physical constraints.