Timing Violations - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

While fixing the worst timing violation often improves overall QoR, you must also review other critical paths, as they frequently contribute to timing closure challenges.

Follow these steps to identify and address timing violations using Report Design Analysis:

  1. Generate the Setup Path Characteristics table by running the following. In this example, the command reports the 50 worst setup timing paths.
    report_design_analysis -max_paths 50 -setup


  2. Review the table to isolate which characteristics are introducing timing violations for each path.
  3. If the violation is caused by a high logic delay percentage (Logic Delay):
    • Check if the path has many levels of logic (Logic Levels).
    • Determine whether constraints or attributes prevent logic optimization (Don't Touch, Mark Debug).
    • Identify cells with high logic delay such as RAMB or DSP.
    • Evaluate whether the path requirement is too tight for the current path topology (Requirement).
  4. If the violation is caused by a high net delay percentage (Net Delay):
    • Look for high fanout nets (High Fanout, Cumulative Fanout).
    • Check whether cells are assigned to several Pblocks that might be placed far apart (Pblocks).
    • Check whether cells are placed far apart (Bounding Box Size, Clock Region Distance).
    • For SSI devices, check whether nets cross SLR boundaries (SLR Crossings).
    • Investigate unusually high net delay values when placement appears correct; see the Congestion section for reference.
  5. If the violation is due to a missing pipeline register in a RAMB or DSP cell:
    • Verify that pipeline registers are enabled for RAMBs or DSP cells.
  6. If the violation is due to high skew (<-0.5 ns for setup and >0.5 ns for hold) (Clock Skew):
    • Check whether the path is a clock domain crossing path (Start Point Clock, End Point Clock).
    • Determine whether the clocks are synchronous or asynchronous (Clock Relationship).
    • Check whether the path crosses I/O columns (I/O Crossings).
  7. Review the Logic Level Distribution table generated for the worst 1000 paths to identify long paths in the design.

  8. Eliminate longer paths where possible to improve overall QoR. Based on your findings, improve the netlist by modifying the RTL, changing synthesis options, or adjusting timing and physical constraints.