Timing Paths Example - Timing Paths Example - 2026.1 English

Timing Paths Example - Timing Paths Example - 2026.1 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID

UG906

Release Date

2026-06-23

Version

2026.1 English

The following figure shows the paths previously described. In this example, the design clock CLK0 serves as the board clock for both DIN and DOUT delay constraints.

Figure 1. Timing Paths Example