Timing Path Details in Vivado IDE - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

The timing path details in the Vivado IDE, shown in the following figure, present the same information as the text report in the previous figure.

Figure 1. Timing Path Details in Vivado IDE

The tool displays the path information in five columns when you use the standard flow, or six columns when you use Incremental Compile:

Location
Shows where the cell or port is placed on the device.
Delay Type
Describes the UniSim primitive and the specific timing arc that the path follows. For a net, this column shows the fanout (fo) and its placement or routing status. A net can be Unplaced, Estimated, or Routed.
  • Unplaced: The driver and the load are not placed.
  • Estimated: The driver, the load, or both are placed. A partially routed net is also reported as estimated.
  • Routed: The driver and the load are both placed, and the net is fully routed.
Incr (ns) (text report) / Delay (IDE report)
Displays the incremental delay associated with a UniSim primitive timing arc or a net. It can also show the delay from a constraint, such as input/output delay or clock uncertainty.
Path (ns) (text report) / Cumulative (IDE report)
Displays the accumulated delay after each segment of the path. On a given line, this value equals the previous cumulative delay plus the current incremental delay.
Netlist Resource(s) (text report) / Logical Resource (IDE report)
Shows the name of the netlist object that the path traverses.
Pin Reuse (Incremental Compile only)
Indicates whether the path is reused from the reference run. Possible values include ROUTING, PLACEMENT, MOVED, and NEW.

Each incremental delay is associated with either rising or falling edge senses.

  • r (rising)
  • f (falling)

The tool determines the initial edge sense based on the launch or capture edge used for analysis. The edge sense can change if an element along the path inverts the signal. For example, a rising edge at the input of an inverter becomes a falling edge at its output. Use edge sense to identify tight path requirements from clock edge inversion along the source or destination clock tree.