Timing Path Characteristics Report - Timing Path Characteristics Report - 2026.1 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
Document ID
UG906
Release Date
2026-06-23
Version
2026.1 English

After you run Report Design Analysis in Timing mode, you can view a report showing characteristics of the ten worst setup paths.

Figure 1. Example Setup Path Characteristics

You can generate this report in either of the following ways:

  • In the Vivado IDE, select Reports > Report Design Analysis.
  • In Tcl, enter the command: report_design_analysis -name <arg>
Tip: To create hold path characteristics, select Path delay type: min in the Options tab of the Report Design Analysis dialog box or add -hold to the Tcl command option. For more information on Tcl command option syntax, refer to the Vivado Design Suite Tcl Command Reference Guide (UG835).

The Logic Level Distribution table shows the distribution of logic levels for the worst timing paths.

Figure 2. Example of Logic Level Distribution Report

Use the following steps to generate the table:

  1. Select Options > Include logic level distribution.
  2. By default, the tool analyzes 1,000 paths. You can change this value in the same tab.

In the GUI, logic level bins now include hyperlinks.

Figure 3. Report Design Analysis on a Selected Path

Click a bin to run report_design_analysis or report_timing on paths in that bin. You can also select specific timing path objects.

Command Line Enhancements for Logic Level Analysis

  • Use -routes with -logic_level_distribution to generate bins based on routing segments instead of logic levels.
  • Use -min_level and -max_level to control which logic levels are grouped into bins.
    • Vivado groups paths with logic levels below -min_level in one bin.
    • Vivado groups paths above -max_level in another bin.
    • All other paths are binned individually by logic level if at least one path exists at that level.
Figure 4. Logic Level Analysis with -routes Enhancements

Figure 5. Logic Level Analysis with -min_level and -max_level Enhancements

For example, if your design has logic levels of 0, 1, 3, 4, 5, 11, 12, 14, 15, and 16, and you specify -min_level 3 -max_level 11, the report creates bins 0–2, 3, 4, 5, 11, and 12+. Refer to Timing Path Characteristics Report for reference.