After you run Report Design Analysis in Timing mode, you can view a report showing characteristics of the ten worst setup paths.
Figure 1. Example Setup Path Characteristics

You can generate this report in either of the following ways:
- In the Vivado IDE, select .
- In Tcl, enter the command:
report_design_analysis -name <arg>
Tip: To create hold path characteristics,
select Path delay type: min in the
Options tab of the
Report Design Analysis
dialog box or add
-hold to the Tcl command option. For more
information on Tcl command option syntax, see the
Vivado
Design Suite Tcl Command Reference Guide (UG835).The Logic Level Distribution table shows the distribution of logic levels for the worst timing paths.
Figure 2. Example of Logic Level Distribution Report

To generate this table:
- Select .
- By default, the tool analyzes 1,000 paths. You can change this value in the same tab.
In the GUI, logic level bins now include hyperlinks.
Figure 3. Report Design Analysis on a Selected Path

Click a bin to do one of the following:
- Run
report_design_analysisorreport_timingon paths in that bin. - Select specific timing path objects.
Command Line Enhancements for Logic Level Analysis
- Use
-routeswith-logic_level_distributionto generate bins based on routing segments instead of logic levels. - Use
-min_leveland-max_levelto control which logic levels are grouped into bins.- Paths with logic levels below
-min_levelare grouped in one bin. - Paths above
-max_levelare grouped in another. - All other paths are binned individually by logic level if at least one path exists at that level.
- Paths with logic levels below
Figure 4. Logic Level Analysis with

-routes
Enhancements
Figure 5. Logic Level Analysis with

-min_level and
-max_level Enhancements
For example, if your design has logic levels of 0, 1, 3, 4, 5, 11,
12, 14, 15, and 16, and you
specify:
-min_level 3 -max_level 11The
report creates these bins: 0–2, 3, 4, 5, 11, and 12+. See Timing Path Characteristics Report for reference.