Timing Field - 2025.2 English - UG906

Follow these steps to configure the Timing field in the Report Design Analysis dialog box:

1. Enable timing analysis by ticking the Timing checkbox to report timing and physical characteristics of timing paths.

   Equivalent Tcl option: -timing

2. Choose between All Paths or Specific Paths analysis:
   • If analyzing all paths:
     1. Select All Paths.
     2. Choose a delay type:
        • max for setup
        • min for hold
        • min_max for both setup and hold

        Equivalent Tcl options: -setup, -hold

     3. Set the Maximum Number of Paths per Clock Group (default is 10).

        Equivalent Tcl option: -max_paths <arg>

   • If analyzing a specific path:
     1. Select Specific Paths.
     2. Click Browse to open the search dialog box and select timing path objects.

     3. For more on selecting paths, see the get_timing_paths command in UG835.

     Equivalent Tcl option: -of_timing_paths <args>

     For more information about get_timing_paths, refer to get_timing_paths in the Vivado Design Suite Tcl Command Reference Guide (UG835).

3. (Optional) Enable Extend Analysis by selecting Extend Analysis. This analyzed each path of interest along with:
   • The worst path to the startpoint
   • The worst path from the endpoint
   This helps determine whether hold fixes are affecting setup timing.

   Equivalent Tcl option: -extend

4. (Optional) Include logic-level distribution by selecting the Logic-Level Distribution option and specify how many paths to include.
   • If you selected All Paths, this number overrides the max paths per clock group.
   • If you selected Specific Paths, logic-level distribution applies only to those paths.

   Equivalent Tcl options:

   • -logic_level_distribution
   • -logic_level_dist_paths <arg>