The AMD Vivado™ Integrated Design Environment (IDE) provides several reporting commands to help you verify that your design meets all timing constraints and is ready to load onto the application board.
Use the Report Timing Summary for timing signoff. This report gives you a comprehensive overview of all timing checks and includes enough details to help you begin analyzing and debugging any timing issues. For additional insight, refer to the Logic Analysis in the IDE.
You can:
- View the report in a window.
- Write it to a file.
- Print it to your log file.
If the Report Timing Summary shows that your design fails to meet timing or is missing constraints, do the following:
- Review the detailed sections of the summary.
- Use the information to run more specific analysis.
You can use other timing reports to:
- Focus on a particular issue.
- Narrow the scope of analysis using filters and scoping capabilities.
Before adding timing constraints, take time to understand the fundamentals of timing analysis and the key terminology used by the Vivado IDE timing engine. This chapter introduces those core concepts.