Timer Settings Tab - 2025.2 English - UG906

Follow these steps to configure the timer settings in the Report Design Analysis dialog box:

1. Select the Interconnect:

   actual

   Applies accurate interconnect delays for a fully routed design.

   estimated

   Uses estimated interconnect delays based on placement and connectivity, even for routed designs.

   none

   Ignores interconnect delays and uses only logic delays, which can help identify paths dominated by logic delay

   Equivalent Tcl command option: set_delay_model -interconnect <arg>

   For more information about set_delay_model, refer to the Vivado Design Suite Tcl Command Reference Guide (UG835).

2. Select the Multi-Corner Configuration to limit the default four-corner analysis performed by the timing engine. Adjust the corners and delay types based on your analysis needs.

   Equivalent Tcl command option: config_timing_corners -corner <arg> -delay_type <arg>

3. Select Disable Flight Delays if you want to exclude package delays from I/O timing calculations.

   Equivalent Tcl command option: config_timing_analysis -disable_flight_delays <arg>

   
   
   

For more information about these Tcl command options, refer to the Vivado Design Suite Tcl Command Reference Guide (UG835).