The Vivado synthesis log is the primary output from the synthesis tool. It includes details such as:
- Files processed:
- VHDL
- Verilog
- System Verilog
- XDC
- Parameter settings per cell
- Nets with multiple drivers
- Undriven hierarchical pins
- Optimization information
- Black boxes
- Final primitive count
- Cell usage by hierarchy
- Runtime and memory usage Important: Review this log or the Messages tab for errors, critical warnings, and warnings. The synthesis tool can issue messages that cause serious issues later. Address them early to avoid downstream problems.