It can be useful to analyze a design based on connectivity. Use Show Connectivity to review the placement of all logic driven by a selected cell or net.
- Select one or more cells or nets.
- Run Show Connectivity to expand the selection by including connected cells or nets.
Tip: Use this method to build and
view cones of logic inside the design.
The following figure shows a block RAM driving logic inside the device including OBUFs. A synthesis pragma prevents synthesis from placing the output flop in the block RAM during memory inferencing.
Figure 1. Show Connectivity
