You can use Show Connectivity to analyze a design based on connectivity. This command lets you review the placement of all logic driven by a selected cell or net.
- Select one or more cells or nets.
- Right-click the selection and click Show Connectivity.
Vivado expands the selection to include connected cells or nets.
Tip: Use this method to build and
view cones of logic inside the design.
The following figure shows a block RAM driving logic inside the device, including OBUFs. A synthesis pragma prevents synthesis from placing the output flop in the block RAM during memory inferencing.
Figure 1. Show Connectivity
