Setup/Hold for Input Buses - 2025.2 English - UG906

Vivado automatically detects input buses and reports the following:

• Worst-case setup and hold values
• Worst Case Data window = largest setup + largest hold
• Slack (if input ports are constrained)
• Optimal tap point (if IDELAY is used) for balanced setup and hold. The optimal tap point can be used to configure IDELAY for balanced setup and hold slack.
• Source offset = difference between the setup/hold window and the window defined by input delay and clock period. If the input clock is offset with this value, then it is be in the center of the window.

The following figure reports a design in which a DDR input bus, vsf_data[0:9], has a worst case data window of 1.663 ns. The ideal clock offset is 1.063 ns.

Figure 1. Setup and Hold Delays for Input Buses

set_property IDELAY_VALUE 13 [get_cells idelay_clk]