SLR Crossings by Logic Level - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

You use the SLR Crossing by Logic Level table to analyze the performance of SLR crossings on timing paths. The table presents the data on a clock-by-clock basis. It contains the following information:

  • The clock group name based on endpoint clock
  • The requirement of the paths listed in the row. A clock group can have more than one row if there are different requirements for the timing paths caused by for example, a timing exception.
  • The WNS of the crossing SLR paths. This might not be the WNS of the clock group as a whole.
  • Calibrated deskew usage
  • The clock vtree template used
  • The clock root
  • The clock expansion window
  • Logic level bins
The following is an example of the report table with the clock information columns removed :

4. SLR Crossings by Logic Levels
--------------------------------

+--------+-------------+--------+-------------++------+------+
| Clock  | Requirement | WNS    | GCLK_DESKEW || 0    | 1    |
+--------+-------------+--------+-------------++------+------+
| clka   | 8.000       | 0.650  | CALIBRATED  ||  434 |    0 |
| clka   | 4.000       | 1.054  | CALIBRATED  ||   63 |  125 |
| clkc   | 3.000       | 0.022  | Off         || 5131 |  205 |
+--------+-------------+--------+-------------++------+------+
Note: Because this report is timing-path based, count n paths that cross an SLR on the same SLL when the fanout is greater than one. The number of timing paths is adjusted based on the number of crossings, but you might not capture every timing path that crosses an SLR. The timing paths used in the report are ordered by WNS with the worst slack paths being used.

For AMD UltraScale™ and AMD UltraScale+™ designs, first evaluate the Requirement and WNS columns to determine whether the timing requirements are both realistic and achieved. If the requirements are realistic but timing is not met, use the Logic Levels section to gain insight into possible issues. In that case, evaluate the other tables to examine the design partition.

For AMD Versal™ designs, when WNS is less than 0.000, add the additional step of reviewing the reported clocking structures. Evaluate whether you can optimize the clocking structure for SLR crossings. Perform this step before reviewing any partitions. See Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388) for more information.

You can conduct further analysis on the specific paths by following the instructions provided in the table footer.