SLR Crossing by Fanout - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

The SLR Crossing by Fanout table shows the fanout of nets that cross between SLRs. It is ordered based on highest fanout first. It gives the following information:

  • The total fanout of the net
  • Driver cell type
  • The SLR load distribution and an indicator of SLR driving region
  • The net name
The following shows an example of a report:
5. SLR Crossings by Fanout
--------------------------

+--------+-------------+------+------+------+------+------------+
| Fanout | Driver Type | SLR0 | SLR1 | SLR2 | SLR3 | Net Name   |
+--------+-------------+------+------+------+------+------------+
|    378 | FDRE        |    0 |   9* |  369 |    0 | net_name1  |
+--------+-------------+------+------+------+------+------------+
* Indicates driver region
In this example, the driver is in SLR1, as indicated by the *. There are nine loads in the same SLR, and 369 loads in SLR2, giving a total fanout of 378. The net is called net_name1.

When your net has a high fanout, you can experience some difficulty optimizing for both fanout and SLR crossing. This depends on a combination of the design structure (for example, whether the net is driven by a register such as FDRE or FDCE), the timing requirement, and the tool options you select. You can resolve most issues by increasing the effort levels for place_design and phys_opt_design, and by using FORCE_MAX_FANOUT properties to further replicate.

Timing penalties incur on every timing path that has the source in one SLR and the load(s) in another. As long as the paths are timed, the challenge increases when more loads are in a different SLR from the driver, compared to a net with the same fanout profile but with most loads placed in the same SLR.

To find timing information on the net, use the report_timing command. For example:
report_timing -name slr_xing_hfn -through [get_nets net_name1] -setup
Note: See the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388) for guidance on using properties to replicate the nets based on SLR load placement.