Resolution - Resolution - 2026.1 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2026-06-23
Version
2026.1 English

The solution depends on whether the two clock domains are asynchronous or synchronous.

  • If asynchronous, cover the paths between the two domains with a timing exception such as:
    set_max_delay -datapath_only ...
    set_clock_groups ...
    set_false_path ...
    
  • If synchronous, adjust the clock constraints to correctly define the relationship between the two clocks.