Resolution - Resolution - 2026.1 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2026-06-23
Version
2026.1 English
Because the waveforms do not allow safe timing analysis between the two clocks, treat these clocks as asynchronous. Cover the paths between the two clock domains with a timing exception such as:
set_max_delay -datapath_only ...
set_false_path ...
set_clock_groups ...