Resolution - Resolution - 2026.1 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2026-06-23
Version
2026.1 English

Remove the set_false_path, set_clock_group-asynchronous, or set_max_delay -datapath_only constraints between the synchronous clocks. If the clocks are truly asynchronous, add an asynchronous clock constraint and implement proper synchronization circuitry for the asynchronous clock domain crossing. To determine whether a clock domain crossing is synchronous or asynchronous, use the clock interaction report.