Resolution - 2025.1 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-05-29
Version
2025.1 English

Remove the false_path, set_clock_group -asynchronous, or set_max_delay -datapath_only constraints that are applied between the synchronous clocks. If the clocks are expected to be asynchronous, add an asynchronous clock constraint with the proper synchronization circuitry for the asynchronous clock domain crossing.

To understand which clock domain crossing is synchronous or asynchronous, follow the clock interaction report.