Resolution - Resolution - 2026.1 English - UG906

The resolution depends on whether the clock domains are asynchronous or synchronous:

• If asynchronous clocks, cover all paths between the two domains with a timing exception such as:

  set_max_delay -datapath_only ...
  set_clock_groups ...
  set_false_path ...
  

• If synchronous clocks, you can waive this check.

If the violation occurs during out-of-context (OOC) synthesis of a module, and the two clocks have a common node at the top level, you can prevent the violation during OOC synthesis by:

1. Defining one of the clocks as a primary clock on the first input clock port.
2. Defining the second clock as a generated clock on the second input clock port, referencing the primary clock from step 1.
3. Defining the HD.CLK_SRC property on both input clock ports.