If the clock domain crossing between the parallel PLLs is intended to be synchronous, set DIVCLK_DIVIDE to 1 on each CMB. If the crossing is intended to be asynchronous, update the timing constraints to reflect an asynchronous clock domain crossing and add the appropriate synchronization circuitry in the destination clock domain. For more details, refer to UltraFast Design Methodology Guide for FPGAs and SoCs (UG949).