The resolution depends on whether the two clock domains are asynchronous or synchronous. In the case of the clocks being asynchronous, the paths between the two domains should be covered by a timing exception (such as set_max_delay -datapath_only, set_clock_groups, or set_false_path).
In the case of the clocks being synchronous, this DRC warning can be waived.
When the violation is reported during the OOC (Out-Of-Context) synthesis of a module and if the two clocks are known to have a common node at the top-level, the TIMING-7 violation can be prevented by the steps outlined below:
- Define one of the clocks as a primary clock on the first input clock port.
- Define the second clock as a generated clock on the second input clock port. This clock should reference the primary clock defined in step 1.
- Define the property HD.CLK_SRC on the two input clock ports.