Resolution - Resolution - 2026.1 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2026-06-23
Version
2026.1 English

Remove the primary clock definition on the hierarchical pin. If a downstream clock is required, use a create_generated_clock constraint with the driver clock specified as the master clock instead.