Resolution - 2025.1 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-05-29
Version
2025.1 English

As the waveforms do not allow safe timing analysis between the two clocks, it is recommended to treat these clocks as asynchronous. Therefore, the paths between the two clock domains should be covered by a timing exception (such as set_max_delay -datapath_only, set_false_path, or set_clock_groups).