Report Utilization - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

The utilization report helps you analyze how your design uses resources at the hierarchical level, within user-defined Pblocks, or across super logic regions (SLRs). You can generate this report at various stages in the flow using the report_utilization Tcl command. For detailed syntax and options, refer to the Vivado Design Suite Tcl Command Reference Guide (UG835).

The following details apply to AMD UltraScale™ and AMD UltraScale+™ families. Each report includes the target device and shows utilization for the following categories:

  • Netlist Logic
    • LUT
    • MuxFx
    • Register
    • LUT as memory
    • LUT flip-flop pairs
    • LUT as logic
    • Carry logic
    Additional items might appear in each category depending on the design.
  • CLB Distribution: Provides details on how the logical netlist maps to physical sites after placement. This includes:
    • Slice
    • LUT combining information:
      • Use of O5 and O6 for UltraScale+ and earlier
      • Dual output LUT for AMD Versal™
    • Packing details for LUT and register pair usage
    • Control sets
  • BLOCKRAM
    • BlockRAM
    • UltraRAM
    • FIFO
  • ARITHMETIC
    • DSP resources
  • I/O Resources
  • Clocking Resources
  • Specific Device Resources (for example):
    • STARTUPE2
    • XADC
  • Primitive Type Count: sorted by usage
  • Black Boxes
  • Instantiated Netlists
  • SLR Crossing Utilization

When you run the command from the Tcl Console, you can scope the resource usage for a specific hierarchical cell using the -cells option. When you run it from the AMD Vivado™ Integrated Design Environment (IDE), the tool displays this information in an interactive table.

Resource numbers might change throughout the flow as logic optimization commands modify the netlist.