Report Timing Summary - Report Timing Summary - 2026.1 English - UG906

You can perform timing analysis at any point after synthesis. You can review the Timing Summary report files that synthesis and implementation runs generate automatically.

Use the following steps to generate a Timing Summary report:

1. Load a synthesized or implemented design into memory.
2. Use one of the following options in the Vivado IDE:
   • Click Flow Navigator > Synthesis
   • Click Flow Navigator > Implementation
   • Select Reports > Timing > Report Timing Summary
3. In Tcl, run the command report_timing_summary.
4. Review the interactive report that appears.

For more information, refer to report_timing_summary in the Vivado Design Suite Tcl Command Reference Guide (UG835).

Use the following guidelines to understand report accuracy:

• In a synthesized design, the AMD Vivado™ IDE timing engine estimates net delays from connectivity and fanout.
• You get more accurate delay estimates for nets between cells you already placed.
• You can see larger clock skew on paths with only pre-placed cells, such as I/Os and GTs.
• In an implemented design, Vivado calculates net delays from actual routing information.
• You must use the Timing Summary report for timing signoff after complete routing.

To verify that routing is complete, open the Route Status report.

Use the following instructions to generate a scoped Timing Summary report:

1. Run the report from the Tcl Console or GUI.
2. Use the -cells option to scope the report to one or more hierarchical cells.
3. Review the report. The report shows only paths whose datapath section starts, ends, crosses, or stays fully within the specified cells.

Use the following guidelines for the methodology summary section:

• When you run report_timing_summary from the Tcl Console, the first section summarizes methodology violations from the latest report_methodology run.
• When you run the report from the GUI, this section appears as Methodology Summary.
• If you did not run report_methodology first, this section appears empty.
• If the design changed after the last report_methodology run, the violations summary might be outdated. Run report_methodology again to ensure accuracy.