Report Timing Summary - 2025.2 English - UG906

Timing analysis is available at any point in the flow after synthesis. You can review the Timing Summary report files that are automatically generated during the Synthesis and Implementation runs.

Use the following instructions to generate a Timing Summary report:

1. Load a synthesized or implemented design into memory.
2. In the Vivado IDE, do one of the following:
   • Click Flow Navigator > Synthesis
   • Click Flow Navigator > Implementation
   • Select Reports > Timing > Report Timing Summary
3. In Tcl, run the command report_timing_summary.
4. Review the interactive report that appears.

For more information, see report_timing_summary in the Vivado Design Suite Tcl Command Reference Guide (UG835).

In a synthesized design, the AMD Vivado™ IDE timing engine estimates net delays based on connectivity and fanout. You get more accurate delay estimates for nets between cells that you have already placed. However, you might see larger clock skew on paths where some cells, such as I/Os and GTs, are only pre-placed.

In an implemented design, the tool calculates net delays based on actual routing information. You must use the Timing Summary report for timing signoff after the design is completely routed.

To verify that routing is complete, open the Route Status report.

Use the following instructions to generate a scoped Timing Summary report:

1. Run the report from the Tcl Console or GUI.
2. Use the -cells option to scope the report to one or more hierarchical cells.
3. Review the report. The only paths that are reported are the ones where the datapath section starts, ends, crosses, or is fully contained within the specified cells.

When you run report_timing_summary from the Tcl Console, the first section of the report shows a summary of methodology violations from the latest report_methodology run. When you run the report from the GUI, this section appears as Methodology Summary.

• If you have not run report_methodology before generating the Timing Summary, this section appears empty.
• If the design has changed because the last report_methodology run, the violations summary might be outdated. Run report_methodology again to ensure accuracy.