Run the super logic region (SLR) crossing report to conduct a detailed analysis of the SLR crossing nets and their timing paths. Only run it on placed designs that use parts with more than one SLR. You can use it to review the following:
- Utilization of super long lines (SLLs) between different SLRs
- Utilization of different sites in each SLR
- Timing performance per clock on paths that cross SLR
- Nets with high fanout that cross SLR and their load distribution in each SLR
- The design hierarchy of the drivers to see which hierarchies are on the boundary of a crossing and the driver's primitive type
For information on the following tables, refer to Show SLR Utilization from report_utilization.
- SLR connectivity
- SLR connectivity matrix
- SLR CLB logic and dedicated block utilization