Report Pulse Width - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English
Figure 1. Report Pulse Width

The Pulse Width Report checks whether your design meets the following requirements for each instance clock pin:

  • Minimum period
  • Maximum period
  • High pulse time
  • Low pulse time

It also verifies that the maximum skew requirement is met between two clock pins of the same instance in the implemented design (such as PCIe clocks).

The report does not include jitter or clock uncertainty in the slack calculations.

To generate this report:

  1. Use the Tcl command: report_pulse_width
  2. Use the -cells option to scope the report to specific hierarchical cells
    • Only pins within the selected cells are included
    • This option is not available in the Report Pulse Width GUI
Note: In the AMD Integrated Software Environment (ISE) Design Suite, this check was previously called Component Switching Limits.