Report High Fanout Nets Options - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

Name

In the Results Name field at the top of the Report High Fanout Nets dialog box, specify the name of the graphical window for the report.

The equivalent Tcl command option is:

-name <windowName>

Fanout

You can set minimum and maximum limits to only report nets within a fanout range.

The equivalent Tcl command options where <n> is the number you specify, are:

-fanout_greater_than <n>
-fanout_lesser_than <n>

Objects

Hierarchical cells:

You can limit the the High Fanout nets report by hierarchical cell objects. Only nets with sources inside the specified cell are reported.

The equivalent Tcl command option is:

-cells [get_cells <hierarchical cell>] 

Clocks:

By default clocks are excluded from the high fanout report. Use -clocks to add reporting of clocks to the report.

The equivalent Tcl command option is:

-clocks [get_clocks <clock object>] 

Max Nets

By default, the report includes 10 nets. You can change this number by using the -max_nets switch. To include the worst-case slack for each net, add the -timing switch to the command.

The equivalent Tcl command options are:

-max_nets <n>
-timing

Load Distribution

You can add load types, clock regions, and SLRs to the report. To include all three, run the command multiple times, each with a different switch.

The equivalent Tcl command options are:

-load_types 
-clock_regions 
-slr 

Histogram

You can display a histogram that shows fanout counts and the number of nets in each bucket. Use this histogram to determine whether a high number of lower fanout nets could pose a problem. This table is available only in text mode.

To generate it, use the -histogram switch.

Figure 1. Histogram Table

The equivalent Tcl command option is:

-histogram 
Note: You can also view fanout in timing reports for each net. To check fanout directly, use the FLAT_PIN_COUNT property on the net.

To address high fanout issues, refer to Optimizing High Fanout Nets and High Fanouts in Critical Paths in the UltraFast Design Methodology Guide for FPGAs and SoCs (UG949) or the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388).