Report Control Sets - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

A control set is the unique combination of a clock signal, a clock enable signal, and a set/reset signal. Each slice supports a limited number of control sets, and the allowed combinations vary by architecture. Some sharing is possible within a slice, but you must understand the configurable logic block (CLB) architecture of your target device to follow compatibility rules.

The Control Sets report highlights the following key areas:

Absolute control set count
Each device supports a finite number of control sets. Exceeding the recommended count can negatively affect quality of results (QoR).
Load profile of control sets
When you need to reduce control sets, target those with low load counts. These introduce the least overhead when merged or optimized.

The following is an example of the Control Sets report summary.

Figure 1. Control Set Summary Table

Nets replicated during synthesis tend to overlap and increase routing resource usage. Nets replicated by physical synthesis generally overlap less and can be ignored when counting control sets.

If your design exceeds the recommended control set limit, do the following:

  • Optimize control sets with the lowest basic element of logic (BEL) load counts.
  • Use the histogram summary to assess distribution and identify reduction opportunities.
Figure 2. Control Set Histogram Table

You can refine the report using the following switches:

  • -hierarchical and -hierarchical_depth: scope control set data by design hierarchy
  • BLOCK_SYNTH.CONTROL_SET_THRESHOLD: re-target control sets at specific hierarchy levels

The report also shows the types of flip-flop distribution in use. Vivado cannot re-target asynchronous resets.

Figure 3. Control Set Flip Flop Distribution

To view a complete list of all control sets, use the -verbose switch. This adds the following fields per control set:

Clock Signal
The logical clock signal name
Enable Signal
The logical clock enable signal name
Set/Reset Signal
The logical set/reset signal name
Slice Load Count
The number of unique slices that contain cells connected to the control set
BEL Load Count
The number of cells connected to the control set

Refer to UltraFast Design Methodology Guide for FPGAs and SoCs (UG949) for guidance on recommended control set usage.