The Clock Utilization report helps you analyze how the design uses clocking primitives and routing resources at either the clock region level or the clock net level. You can use this report to debug clock placement issues and identify placement constraints that help maximize resource utilization.
The Clock Utilization Report provides the following information:
- The number of clocking primitives available and used, along with their physical constraints
- The timing clock name and period associated with each clock net
- Clocking and fabric load utilization for each clock region
- The number of loads on each clock net in each clock region
In the Vivado IDE, the Clock Utilization Report also supports selection of netlist and device objects, allowing you to highlight placement details and generate schematics.