RQS_UTIL-10: Incomplete Case Statement Increasing Control Sets - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

When case statements are incomplete, the output retains its previous state, which infers a clock enable. Define all states in the case statement to avoid increasing control sets. For any additional states, assign the output to a previously used signal, a constant 1, or a constant 0 to prevent adding unnecessary logic.

Figure 1. CE Inference Incomplete Case