RQS_TIMING-202: Add Extra Pipelining to Wide Multipliers - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

Wide multipliers, where at least one port exceeds the maximum width supported by the DSP slice in the target architecture, require additional pipeline stages to achieve the maximum operating frequency of the DSP slice. The required number of stages depends on the multiplier width.

Adding extra stages to the output of wide multipliers in the RTL allows the synthesis tool to move them to optimal positions, making recoding straightforward.