RQS_CLOCK-26: Enabling Calibrated Deskew - RQS_CLOCK-26: Enabling Calibrated Deskew - 2026.1 English - UG906

This check creates GCLK_DESKEW = "Calibrated" constraints on high-load, high-performance clocks. By default, clocks are uncalibrated in Versal designs. Updating to calibrated typically lowers skew, increases insertion delay, and improves SLR crossing performance.

The suggestion triggers when all of the following conditions are met:

• The design targets a Versal multi-SLR device.
• Report QoR Suggestions runs after opt_design.
• Up to four clocks can be recommended.
• The clocks are among the top 10 high-fanout clocks in the design.
• The frequency must be above the performance for a balanced clock tree SLR crossing for the targeted part.

In most cases, this check targets only BUFGCE drivers. It does not target BUFG_GT drivers except in very high-load cases.

This check is not offered on clocks that meet any of the following conditions:

• The user has updated the property.
• The clock has registers driving BUFG_FABRIC loads.
• The clock drives loads with I/O timing requirements.
• The clock has related clocks, unless they are synchronous CDCs driven by an MBUFG.

This suggestion has higher priority than RQS_CLOCK-25. When RQS_CLOCK-26 is offered on a clock net, RQS_CLOCK-25 is not recommended.

The following is a related suggestion: RQS_CLOCK-25